High Performance Reconfigurable Computing

Project Code: 812

Faculty: Faculty of Engineering

Department: Electrical & Computer Engineering

Main Supervisor: Dr Oliver Sinnen

Application open date: 01 Sep 2019

Application deadline: 01 Dec 2022

Enrolment information: NZ Citizens, NZ Permanent Residents, International

Introduction

A reconfigurable hardware system constructed from FPGAs (often in combination with general purpose processors) can provide much higher performance than general purpose parallel systems. The advantage comes from the potentially much higher concurrency of many small processing elements that can work in parallel. Unfortunately, configuring a reconfigurable system is even more challenging than programming a parallel system. The Parallel and Reconfigurable Computing lab investigates high-level approaches to configuring (or "programming") of such reconfigurable systems, hardware data structures and algorithms, and the use of reconfigurable for certain application areas such as radio astronomy or bioengineering. The research in this area deals with hardware design, OpenCL, compiler construction, domain specific high level synthesis, scheduling/mapping and parallelisation techniques. Several PhD and ME projects are available.

 

What we are looking for in a successful applicant

Important knowlege and skills include:

  • hardware design
  • HDL languages
  • algorithm design
Objective

The research in this area by the Parallel and Reconfigurable Computing lab comprises different objectives, including:

  • advances in high level synthesis (HLS)
  • modulo scheduling
  • domain-specific high level synthesis
  • hardware implementation of radio astronomical algorithms
  • OpenCL as cross FPGA high level approach
  • Square Kilometre Array (SKA)
Other information
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